01 AUG 2025 — PRESENT
REDACTED FEED SEIZED // SEC LEVEL RESTRICTED

Electrical Engineer I

Northrop Grumman · Apopka, FL

RTL design, SoC integration, hardware bring-up, and qualification test for a space-qualified imaging program.

Details
  • Designed a runtime-reconfigurable RTL sensor-emulation module (VHDL, PolarFire FPGA, AXI-Stream) for a space-qualified imaging system — adopted as the program's primary verification stimulus, unblocking downstream work ahead of real sensor hardware.
  • Brought up a mixed-signal Ethernet data path (SGMII PHY, RISC-V softcore) to stable 1 Gbps, then isolated a TX/RX pin-mapping defect that was silently dropping packets before it reached production hardware.
  • Built a three-solenoid lifecycle qualification rig — custom protection circuitry, MSP430 firmware, synchronized DAQ/scope/UART — running 5-million-cycle campaigns at 2× projected mission life and cutting the qualification schedule roughly threefold.
02 MAY 2025 — AUG 2025
REDACTED FEED SEIZED // SEC LEVEL RESTRICTED

Electrical Engineering Intern

Northrop Grumman · Apopka, FL

Thermal test hardware and EMI validation support for pre-production programs.

Details
  • Designed and built an electrical system providing uniform thermal distribution across a test target, supporting validation of an emerging defense technology.
  • Created drawings and assembled wiring harnesses for EMI testing of pre-production programs.
03 SEP 2024 — MAY 2025
Pending Upload IMG // NO PREVIEW

Undergraduate Researcher

UCF HAVEN Lab (Hardware Security & Verification Automation) · Orlando, FL

Applied LLMs to automated RTL security analysis for a RISC-V SoC.

Details
  • Built an LLM-based RTL security analysis pipeline, fine-tuning GPT-4 and Llama models to flag hardware vulnerabilities at the register-transfer level against the CWE taxonomy.
  • Validated AI-flagged weaknesses with UVM testbenches, confirming they were reachable rather than false positives.
04 MAY 2024 — AUG 2024
REDACTED FEED SEIZED // SEC LEVEL RESTRICTED

Electrical Engineering Intern

Northrop Grumman · Apopka, FL

Qualification testing for FPGA upgrades and MIL-STD-810G shock-test hardware.

Details
  • Qualification-tested FPGA upgrades against program and industry standards.
  • Designed embedded hardware for a MIL-STD-810G Method 516 drop-test platform, verifying compliance under mechanical shock.
  • Built a run-box interface system that streamlined qualification and improved test throughput.