Digital Design Engineer
FPGA design and (Future) ASIC Design. Based in Orlando, FL.
See what I'm building↓
CURRENTLY BUILDING
GISC-0 — a real CPU, on real fabric.
A from-scratch pipelined RISC-V core running actual compiled programs on an FPGA, verified with a full UVM testbench, then carried through an open-source flow to real GDSII. Design → verify → tape out.
Core — in design
UVM verification — planned
ASIC tapeout — planned
Follow the build→
ELSEWHERE ON THIS SITE