A from-scratch pipelined RISC-V core running real compiled programs on an FPGA with VGA output, verified with a full UVM testbench against a golden ISS reference model, then taken through an open-source flow to real silicon layout.
A reconfigurable spatial-convolution engine on a Xilinx Artix-7 — one hardware datapath running box blur, Gaussian blur, and Sobel edge detection without resynthesis, streamed through a line-buffer architecture to a PMOD OLED (VGA output to a full monitor next).
Led hardware development of a real-time magnetic field imaging system — an 8×8 Hall-effect sensor array, ESP32 acquisition pipeline, and custom PCBs designed to preserve analog signal integrity across the array.
A UVM-based testbench verifying a one-hot multiplexer with constrained randomization and functional coverage targets, exhaustively exercising every critical path before synthesis.
A battery-powered ultrasonic range finder on an MSP430FR6989 — I²C/UART sensor interfacing and dual-rail boost regulation, measuring range to ±0.3 cm precision.
VHDL · Verilog · SystemVerilog · UVM · QuestaSim
Vivado · Libero SoC · SmartDesign · Cadence Allegro · SoftConsole
Cadence Virtuoso · Full-custom VLSI design · CAD for VLSI
PolarFire · Artix-7 · RISC-V MI-V · MSP430 · ESP32
Embedded C · bare-metal · interrupts · UART · I²C · SPI
AXI-Stream · SGMII · RGMII · JTAG · LVDS · DDR
C · Python · VHDL · Verilog · SystemVerilog · TCL