GISC-0.
A real CPU, on real fabric.
Not an emulator, not a simulation running on someone else's silicon — a pipelined processor implemented in RTL, running real compiled programs, on hardware I own. Designed once, proven three ways: it runs, it's verified, and it tapes out.
A real pipeline, not a toy.
GISC-0 implements the RV32I base instruction set — a deliberate choice over a fully custom ISA. It means a real, free compiler toolchain can produce programs to actually run on it, and a trusted reference model exists to check the implementation against, instruction by instruction. The microarchitecture — the pipeline, the hazard handling, the memory system, the peripheral integration — is original design work built on top of that standard.
Classic 5-stage pipeline: fetch, decode, execute, memory, writeback. Full data forwarding, load-use stalling, and branch resolution — the structure that makes a CPU project actually worth verifying, instead of one that's correct by accident.
Core RTL — in designReal programs. A real display.
Synthesized onto a Digilent Basys3 (Xilinx Artix-7), driving its native VGA port from a memory-mapped framebuffer that a program actually running on the core writes to — not a canned test pattern. Interactive input is the stretch goal: an interim path (onboard switches, or UART-fed input) gets the core interactive early, with real USB HID keyboard/mouse support layered in if it proves tractable in the time available.
The core RTL stays free of FPGA-specific primitives, so the same design retargets to the ASIC flow below without a rewrite.
VGA output — plannedVerified, not assumed.
A UVM environment checks the pipelined core against a trusted golden reference — the Spike RISC-V ISS (or an equivalent instruction-set simulator) — comparing architectural state after every retired instruction, not just at the end of a test. Constrained-random instruction sequences are biased toward exactly the scenarios that break pipelines: back-to-back dependent instructions, load-immediately-followed-by-use, branches near flush boundaries.
The goal isn't "it passed some tests." It's a closed functional-coverage model with a real number attached, and — if the testbench does its job — at least one documented bug it caught that directed testing would have missed.
UVM environment — plannedRTL to GDSII.
The verified core goes through OpenLane/OpenROAD against the open SkyWater Sky130 PDK — synthesis, floorplan, place & route, and DRC/LVS sign-off, entirely open-source. The output is real, fabricatable GDSII, not a rendering. The floorplan below is a placeholder for a real KLayout render of that GDSII, treated with the same iridescent shimmer real silicon shows in hand — swapped in once the layout exists.
OpenLane flow — plannedReal numbers only.
Every figure here traces back to an actual measurement, recorded as it's captured — CPI from simulation, Fmax from timing closure, area and power from sign-off. No estimates presented as measurements, and no gaps filled with guesses.
More is landing here as it's built.
This page updates as each phase actually happens — no roadmap fiction, just the real build in order.